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D

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Diffie-Hellman key agreement

by Yee Wei Law - Tuesday, 30 May 2023, 11:21 PM
 

The Diffie-Hellman (D-H) key agreement (often called “key exchange”) protocol is standardised in NIST SP 800-56A [BCR+18].

The protocol originated in the seminal 1976 paper by Whitfield Diffie and Martin Hellman [DH76], both recipients of the 2016 Turing Award (their contribution took 40 years to be recognised).

Protocol between 👩 Alice and 🧔 Bob [KL21, CONSTRUCTION 11.2] in Fig. 1:

  1. On input of security parameter , 👩 Alice runs probabilistic polynomial-time (PPT) algorithm to obtain the domain parameters , where is a cyclic group of prime order , and is a generator of .

    The bit-length of = the security parameter .

    The domain parameters can be pre-distributed.

  2. 👩 Alice chooses , , uniformly at random, and computes .

    is the (cyclic) group of integers modulo .

    👩 Alice’s (ephemeral) private key and public key are and respectively.

  1. 👩 Alice sends to 🧔 Bob.
  2. 🧔 Bob chooses , ,  uniformly at random, and computes .

    🧔 Bob’s (ephemeral) private key and public key are and respectively.

  3. 🧔 Bob sends to 👩 Alice and outputs .
  4. 👩 Alice computes .

Successful completion of the protocol results in the session key .

Fig. 1: The D-H key agreement protocol [KL21, FIGURE 11.2].

A necessary condition for preventing a probabilistic polynomial-time (PPT) eavesdropper from computing the session key is that the computational Diffie-Hellman (CDH) problem is hard:

Definition 1: Computational Diffie-Hellman (CDH) problem [Gal12, Definition 20.2.1]

Given the triple of elements of , compute .

However, the hardness of the CDH problem is not sufficient.

Just as indistinguishability plays an essential role in symmetric-key encryption, indistinguishability is key here: if the session key is indistinguishable from an element chosen uniformly at random from , then we have a sufficient condition for preventing a PPT eavesdropper from computing the session key [KL21, pp. 393-394].

The indistinguishability condition is equivalent to the assumption that the decisional Diffie-Hellman (DDH) problem is hard:

Definition 2: Decisional Diffie-Hellman (DDH) problem [Gal12, Definition 20.2.3]

Given the quadruple of elements of , determine whether or not.

The DDH problem is readily reducible to the CDH problem, since any algorithm that solves the CDH can compute and compare it with ; implying the DDH problem is no harder than the CDH problem.

In turn, the CDH problem is reducible to the discrete logarithm problem (DLP, see Definition 3), since any algorithm that solves the DLP can compute from , from , and hence ; implying the CDH problem is no harder than the DLP problem.

Definition 3: Discrete logarithm problem (DLP) [Gal12, Definition 13.0.1]

Given , where is a multiplicative group, find such that .

In other words, the DDH problem can be reduced to the CDH problem, which in turn can be reduced to the DLP; solving the DLP breaks the D-H key agreement protocol.

There are multiplicative groups for which the DLP is easy, so it is critical that the right groups are used.

A safe-prime group is a cyclic subgroup of the Galois field with prime order , where is called a safe prime; this subgroup has elements [BCR+18, Sec. 5.5.1.1].

NIST [BCR+18, Appendix D] refers to RFC 3526 and RFC 7919 for definitions of safe-prime groups.

The D-H key agreement protocol is used in the Internet Key Exchange (IKE) protocol, which is currently at version 2 [KHN+14].

References

[BCR+18] E. Barker, L. Chen, A. Roginsky, A. Vassilev, and R. Davis, Recommendation for Pair-Wise Key-Establishment Schemes Using Discrete Logarithm Cryptography, Special Publication 800-56A Revision 3, NIST, April 2018. https://doi.org/10.6028/NIST.SP.800-56Ar3.
[DH76] W. Diffie and M. Hellman, New directions in cryptography, IEEE Transactions on Information Theory 22 no. 6 (1976), 644–654. https://doi.org/10.1109/TIT.1976.1055638.
[Gal12] S. D. Galbraith, Mathematics of Public Key Cryptography, Cambridge University Press, 2012. https://doi.org/10.1017/CBO9781139012843.
[KL21] J. Katz and Y. Lindell, Introduction to Modern Cryptography, 3rd ed., CRC Press, 2021. Available at https://ebookcentral.proquest.com/lib/unisa/detail.action?docID=6425020.
[KHN+14] C. Kaufman, P. E. Hoffman, Y. Nir, P. Eronen, and T. Kivinen, Internet Key Exchange Protocol Version 2 (IKEv2), RFC 7296, October 2014. https://doi.org/10.17487/RFC7296.

E

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Emotet

by Yee Wei Law - Tuesday, 9 May 2023, 2:50 PM
 

First identified in 2014 [ANY14], the Emotet malware evolved from a banking Trojan designed to steal sensitive information (including credentials) to a modular, polymorphic, multi-threat downloader for other, more destructive malware [MGB22].

References

[ANY14] ANY.RUN, Emotet, 2014. Available at https://any.run/malware-trends/emotet.
[MGB22] C. Manaster, G. Glass, and E. Biasiotto, Emotet Analysis: New LNKs in the Infection Chain, The Monitor, Issue 20, May 2022. Available at https://www.kroll.com/en/insights/publications/cyber/monitor/emotet-analysis-new-lnk-in-the-infection-chain.

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Encapsulation Packet Protocol (EPP)

by Yee Wei Law - Sunday, 21 May 2023, 7:43 PM
 

The Encapsulation Packet Protocol (EPP) is used to transfer protocol data units (PDUs) recognised by CCSDS that are not directly transferred by the Space Data Link Protocols over an applicable ground-to-space, space-to-ground, or space-to-space communications link [CCS20b].

References

[CCS20b] CCSDS, Encapsulation Packet Protocol, Recommended Standard CCSDS 133.1-B-3, The Consultative Committee for Space Data Systems, May 2020. Available at https://public.ccsds.org/Pubs/133x1b3e1.pdf.

F

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Flow

by Yee Wei Law - Tuesday, 27 June 2023, 4:24 PM
 

A flow is a set of ordered tuples delineated by a start time and an end time, and having the same 1️⃣ session ID, 2️⃣ protocol type, 3️⃣ source and destination IP addresses, as well as 4️⃣ source and destination ports.

References

[] .

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Hardware Trojan

by Yee Wei Law - Wednesday, 5 April 2023, 10:46 AM
 

A hardware Trojan (see Definition 1) may control, modify, disable, or monitor the contents and communications of the device it is embedded in [RKK14, Sec. II].

Definition 1: Hardware Trojan [RKK14, BDF+22]

Hardware that has been modified with a malicious functionality hidden from the user.

Hardware Trojans provide a means to bypass traditional software and cryptographic-based protections, allowing a malicious actor to control or manipulate device/system software, 1️⃣ getting access to sensitive information, and/or 2️⃣ causing denial-of-service to legitimate users by causing device/system failures or simply by turning the device/system off [BDF+22].

Examples of hardware Trojans are aplenty within academia and outside of academia [HAT21].

💡 It is easier to produce a proof-of-concept for academic publications or demonstrations than executing a real-world attack that has to be robust to diverse usage scenarios.

👩‍🎓 Examples from within academia

Smartphones often break, but replacing broken components provides an opportunity for malicious actors to implant hardware Trojans.

One of the most frequently replaced components is the touchscreen; more than 50% of smartphone owners have damaged their screen at least once [SCSO17].

Steps of the “Shattered Trust” attack [SCSO17]:

  1. A Trojan screen with an embedded microcontroller is installed.
  2. Rogue microcontroller downloads and installs a Trojan app from the Google Play store 🎦.
  3. Trojan app exploits the buffer flow vulnerability CVE-2017-0650 of the Synaptics S3718 device driver, elevating its own privileges to root, disabling SELinux protection and exfiltrating user data including authentication tokens 🎦.
  4. Attacker creates a remote root shell (through ncat for example) to the compromised phone 🎦.

Another frequently replaced component is the phone battery [LFH+18] 🎦.

On a larger scale, computer peripherals can serve as hardware Trojans that exploit the vulnerabilities in Input-Output Memory Management Units (IOMMUs) [MRG+19].

  • An IOMMU is an MMU component that connects a DMA-capable I/O bus to system memory, and maps device-visible virtual addresses to physical addresses; see Fig. 1.
Fig. 1: The IOMMU translates I/O virtual addresses to physical addresses and applies access control, similar to how the MMU translates virtual addresses from processes [MRG+19, Fig. 2].

Watch Christof Paar’s overview lecture:

👩‍💻 Examples from outside academia

In 2018, Bloomberg Businessweek made the sensational claim entitled “The Big Hack” that China’s PLA launched a supply chain attack by implanting a tiny Trojan chip in motherboards made by Super Micro Computer Inc. (“Supermicro” for short)  [MLP+20] 🎦.

  • Supermicro specialises in servers, storage, networking devices, and server management software for data centers and cloud computing.
  • Supermicro motherboards were manufactured by contractors in China, facilitating The Big Hack; see Fig. 2. Supermicro now manufactures motherboards for the US market in the US.
Fig. 2: Alleged steps of The Big Hack [MLP+20, Fig. 3].
  • Elemental Technologies (now AWS Elemental, “Elemental” for short) specialised in developing software to compress large video files (e.g., from the International Space Station, from drones) into formats suitable for handheld devices. This technology attracted partnership from the CIA and Amazon.
  • Elemental used Supermicro’s servers in their data centres.
  • Amazon used Supermicro’s servers in their China-based data centres.
  • Amazon’s security team discovered Trojan chips embedded in the fibreglass layers (upon which other components were attached) with access to the baseboard management controller (BMC), which is the component that enables remote administration.
  • X-ray images captured by Amazon’s security team revealed variations in Trojan chip design, but all resemble signal conditioning couplers.
  • The code in the Trojan chips was small, but it could execute two major tasks: 1️⃣ command the motherboard to communicate with external computers, and 2️⃣ command the operating system to accept new code from said computers.
  • Initial Bloomberg report was met with scepticism, but proofs-of-concept started surfacing soon after.

Trojan detection is challenging because [RKK14, Sec. II]:

  1. The inherent opaqueness of device internals hampers detection of modified components. Reverse engineering is typically resource-intensive and in the worst case destructive.
  2. Technology scaling to the limits of device physics and mask imprecisions cause nondeterminism in a device’s characteristics, rendering distinction between process variations and Trojans challenging.
  3. The infeasibility of characterising the entire behavioural space of a device permits  stealthy implantation of Trojans.

Countermeasures

Four main defence strategies can be identified [HAT21, Sec. 4]:

  1. Design for security: Integrating security right from the beginning is a no-brainer. Three main strategies are identifiable:

    • Secure inter-component communications: While it is impractical to demand all inter-component communications to be encrypted and authenticated, critical processes such as booting should be locked down.

      For example, OpenBMC is a Linux distribution for BMCs used in servers, top-of-rack switches, etc. Since the early 2020s, OpenBMC has been supporting secure boot 🎦.

    • Secure test infrastructure: Lock down the JTAG interface to mitigate the risks of attackers accessing sensitive information and/or compromising system functionality.

      Practicality necessitates a lightweight cryptographic protocol (not TLS). Physical unclonable functions (PUFs) provide a lightweight authentication mechanism.

    • Obfuscation and anti-reverse engineering: Attackers need to understand how a device works before they can implant their hardware Trojan.

      Professional attackers resort to a wide range of reverse engineering techniques [FSK+17, SLP+19]:

      A professional foundry attacker has full knowledge of the circuit layout and hence can extract the transistor-level design directly.

      A professional end-user attacker can de-package, de-layer and image an IC, as per Fig. 3. Further processing of these images can facilitate the reconstruction of the circuit layout.

      The process of layout reconstruction and netlist extraction is referred to as physical reverse engineering.

      Fig. 3: Physical reverse engineering flow: an attacker can de-package, de-layer an IC, and leverage image processing techniques to reconstruct the circuit layout [SLP+19, Fig. 2]. The gate-level netlist can subsequently be extracted.

      Reverse engineering also facilitates IP theft.

      Anti-reverse engineering (anti-RE) techniques include [SLP+19, PP20, HAT21]:

      At the very least, use 1️⃣ more routing layers (especially for sensitive signals) in internal PCB layers, 2️⃣ ICs with ball-grid-array connections, and 3️⃣ extraneous traces, vias and components to confuse adversaries.

      Split manufacturing: Front End of Line (FEOL) layers (transistors and lower metal layers) are fabricated at an untrusted high-end foundry, while the Back End of Line (BEOL) layers (higher metal layers) are manufactured at a trusted low-end foundry; see Fig. 4. This approach hides the BEOL connections from the untrusted foundry.

      IC camouflaging: Using fabrication-level techniques to build circuits whose functionality cannot be easily deduced using nanoscale microscopy and other known physical reverse engineering techniques; see Fig. 5.

      Logic locking: Adding some form of programmability to the design and ensuring that the circuit cannot function properly without the circuit being programmed with a secret string of configuration data referred to as the “key”; see Fig. 5.

      Both IC camouflaging and logic locking are examples of logic obfuscation.

      Fig. 4: Vertical structure of a sample IC showing metal layers (M1 to MX), and vias (V1 to VX-1) connecting adjacent metal layers [PP20, Figure 2]. FEOL layers contain transistors, fabrication of which require a high-end foundry.

      Fig. 5: Examples of logic obfuscation [SLP+19, Fig. 1]: (a) IC camouflaging, where a camouflaging cell that from the top view appears to implement either a NAND or a NOR gate as a substitute for the original gate ; (b) logic locking, where correct key bit at is required to unlock gate . While a key bit has only two possible values, many key bits distributed throughout a circuit can constitute a key of a significant size.

      IC camouflaging requires the fixed obfuscated layout structure to be disclosed to the foundry for fabrication, so IC camouflaging only applies to end-user adversaries.

  2. Manufacturing tests: PCB manufacturers have traditionally relied on electrical, functional, and automated optical testing for quality control.

    While manufacturing tests may detect Trojans with payloads that resemble defects, they are not generally useful for detecting modifications by intelligent adversaries.

    Optical inspection of PCBs uses computer vision and machine learning techniques to identify manufacturing defects on both bare-boards and PCB assemblies:

    • Optical inspection machines are commercially available today, complete with proprietary algorithms that are well-tuned to identifying specific board-level defects such as solder bridging or component misalignment.
    • More advanced optical inspection systems use multiple cameras to construct 3D images of boards to identify problems like lifted leads.
    • X-ray solutions have also been developed to enable inspection of inner-layers of PCB routing.
    • While traditional inspection algorithms are well-tuned to identify defects, these algorithms are not adaptable to identifying Trojan modifications.
    • Developing algorithms suitable for PCB assurance is nontrivial.
  3. Board-level Trojan detection: Going beyond manufacturing tests, specific Trojan detection techniques include:

    • Offline side-channel verification: Similar to ICs, circuit boards have unique signatures that depend on the implemented circuit as well as manufacturing variations.

      Malicious modification to PCB substrate, routing, or components could disrupt these side-channel fingerprints.

      Side-channel disruptions such as resonant frequency and delay patterns of PCB traces can be measured either statically or at run time to identify modified or counterfeit PCBs.

    • Advanced optical inspection: This combines information from multiple imaging modalities to verify components and identify illegitimate modifications.

      Imaging modalities can be classified as per Fig. 6.

      Multi-modal optical inspection is a potentially powerful tool for PCB assurance, and research is evolving quickly.

      Not included in Fig. 6 is quantum diamond microscopy [ATW+22]; see Figs. 7-8.

      Fig. 6: Classification of optical testing methods in terms of imaging modality [HAT21, Fig. 4].
      Fig. 7: Workflow and experimental setup [ATW+22, Fig. 3]: (a) Pseudo-flowchart of a QDM magnetic imaging experiment for Trojan detection. (b) Schematic of the experimental components, where a nitrogen-vacancy diamond is placed directly on a field-programmable gate array (FPGA) containing hardware Trojans at the register transfer level. A 532-nm laser is shone at the diamond at a shallow angle and the resultant red fluorescence is captured on a CMOS camera. The nitrogen vacancies are controlled through the application of external microwaves (MW) and a DC bias magnetic field.
      Fig. 8: The “Neural Network Analysis” block in Fig. 7 can be instantiated as a convolutional autoencoder to perform clustering of image features, for the detection of Trojans [ATW+22, Fig. 1].
  4. Run-time monitoring: Run-time monitoring employs additional hardware to ensure device security in the field.

    • Run-time side-channel verification: Side-channel information such as power consumption of clusters of authentic components on a PCB relative to the total power consumed by the PCB can serve as an indicator of Trojan activity — specifically discrepancies outside a certain tolerance might be worth flagging.

    • Policy engines: A policy engine is an IP block that 1️⃣ monitors bus traffic, 2️⃣ searches for traffic that violates a pre-determined rule or model, and 3️⃣ in case of violation, raises an alert or takes a corrective action.

      On PCBs, a policy engine chip can be installed on buses like PCI and I2C to identify denial-of-service attacks or illegitimate messages.

      For example, the validation tool called ConFirm in Fig. 9 performs computational path analysis with hardware performance counters (HPCs), which are special-purpose registers built into the performance monitoring unit of a modern microprocessor for storing information about hardware events [WKMK15].

      Fig. 9: High-level structure of ConFirm [WKMK15, Fig. 2]. The ConFirm core consists of three components in write-protected non-volatile memory: 1️⃣ an insertion module that inserts checkpoints into the monitored firmware, 2️⃣ an HPC handler that drives the HPCs, and 3️⃣ a database that stores valid HPC-based signatures.

      When an execution checkpoint is reached, the control flow is redirected to the core module. The HPC handler compares the event counts for the previous check window with the corresponding signatures in the database. The HPCs are then reset for the next check window and the execution of the monitored firmware continues until the next checkpoint is reached.

      Fig. 10: Computational path analysis with HPCs [WKMK15, Fig. 1]. The execution of the valid paths and in a monitored subroutine generates HPC vectors and encoding occurrence counts of hardware events. A malicious execution could for example go through path , generating an aberrant vector that is distinguishable from and .

      ARM V8 Cortex-A53 for example has 4 HPCs, and can count 62 types of events.

References

[ATW+22] M. Ashok, M. J. Turner, R. L. Walsworth, E. V. Levine, and A. P. Chandrakasan, Hardware trojan detection using unsupervised deep learning on quantum diamond microscope magnetic field images, J. Emerg. Technol. Comput. Syst. 18 no. 4 (2022). https://doi.org/10.1145/3531010.
[BDF+22] J. C. Booth, M. L. Dowell, A. D. Feldman, P. D. Hale, M. M. Midzor, and N. D. Orloff, 5G Hardware Supply Chain Security Through Physical Measurements, NIST Special Publication 1278, May 2022. https://doi.org/10.6028/NIST.SP.1278.
[FSK+17] M. Fyrbiak, S. Strauß, C. Kison, S. Wallat, M. Elson, N. Rummel, and C. Paar, Hardware reverse engineering: Overview and open challenges, in 2017 IEEE 2nd International Verification and Security Workshop (IVSW), 2017, pp. 88–94. https://doi.org/10.1109/IVSW.2017.8031550.
[HAT21] J. Harrison, N. Asadizanjani, and M. Tehranipoor, On malicious implants in PCBs throughout the supply chain, Integration 79 (2021), 12–22. https://doi.org/10.1016/j.vlsi.2021.03.002.
[LFH+18] P. Lifshits, R. Forte, Y. Hoshen, M. Halpern, M. Philipose, M. Tiwari, and M. Silberstein, Power to peep-all: Inference attacks by malicious batteries on mobile devices, in Proc. Priv. Enhancing Technol., 2018, 2018, pp. 141–158. https://doi.org/10.1515/popets-2018-0036.
[MRG+19] A. T. Markettos, C. Rothwell, B. F. Gutstein, A. Pearce, P. G. Neumann, S. W. Moore, and R. N. M. Watson, Thunderclap: Exploring vulnerabilities in operating system IOMMU protection via DMA from untrustworthy peripherals, in Proceedings of the Network and Distributed Systems Security Symposium (NDSS), February 2019, more information at http://thunderclap.io/. Available at https://www.ndss-symposium.org/wp-content/uploads/2019/02/ndss2019_05A-1_Markettos_paper.pdf.
[MLP+20] D. Mehta, H. Lu, O. P. Paradis, M. A. M. S., M. T. Rahman, Y. Iskander, P. Chawla, D. L. Woodard, M. Tehranipoor, and N. Asadizanjani, The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants, J. Emerg. Technol. Comput. Syst. 16 no. 4 (2020). https://doi.org/10.1145/3401980.
[PP20] T. D. Perez and S. Pagliarini, A survey on split manufacturing: Attacks, defenses, and challenges, IEEE Access 8 (2020), 184013–184035. https://doi.org/10.1109/ACCESS.2020.3029339.
[RKK14] M. Rostami, F. Koushanfar, and R. Karri, A primer on hardware security: Models, methods, and metrics, Proceedings of the IEEE 102 no. 8 (2014), 1283–1295. https://doi.org/10.1109/JPROC.2014.2335155.
[SLP+19] K. Shamsi, M. Li, K. Plaks, S. Fazzari, D. Z. Pan, and Y. Jin, Ip protection and supply chain security through logic obfuscation: A systematic overview, ACM Trans. Des. Autom. Electron. Syst. 24 no. 6 (2019). https://doi.org/10.1145/3342099.
[SCSO17] O. Shwartz, A. Cohen, A. Shabtai, and Y. Oren, Shattered trust: When replacement smartphone components attack, in 11th USENIX Workshop on Offensive Technologies (WOOT), 2017. Available at https://www.usenix.org/system/files/conference/woot17/woot17-paper-shwartz.pdf.
[WKMK15] X. Wang, C. Konstantinou, M. Maniatakos, and R. Karri, ConFirm: Detecting firmware modifications in embedded systems using Hardware Performance Counters, in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, pp. 544–551. https://doi.org/10.1109/ICCAD.2015.7372617.

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Hash functions

by Yee Wei Law - Monday, 23 October 2023, 10:29 PM
 
See 👇 attachment or the latest source on Overleaf.
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Homodyne vs heterodyne detection

by Yee Wei Law - Wednesday, 8 February 2023, 11:42 AM
 

Homodyne detection = method of detecting a weak frequency-modulated signal through mixing with a strong reference frequency-modulated signal (so-called local oscillator).

References

[ETS18] ETSI, Quantum Key Distribution (QKD); Vocabulary, Group Report ETSI GR QKD 007 v1.1.1, December 2018. Available at https://www.etsi.org/deliver/etsi_gr/QKD/001_099/007/01.01.01_60/gr_qkd007v010101p.pdf.

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Intrusion detection: an introduction

by Yee Wei Law - Wednesday, 14 June 2023, 3:57 PM
 

NIST defines intrusion detection to be:

Definition 1: Intrusion detection [SM07, Appendix A]

The process of monitoring the events occurring in a computer system or network and analysing them for signs of possible incidents.

Intrusion prevention goes beyond intrusion detection, although “prevention” is strictly speaking an exaggeration:

Definition 2: Intrusion prevention [SM07, Appendix A]

The process of monitoring the events occurring in a computer system or network, analysing them for signs of possible incidents, and attempting to stop detected possible incidents.

In Definition 2, an “attempt” can be sending an alarm to the administrator(s), resetting a network connection, reconfiguring a firewall to block traffic from the source address, etc.

Thus, “intrusion detection and prevention system” (IDPS) is synonymous with “intrusion prevention system” (IPS) [SM07, Appendix A], and is a bit of a redundant term.

Fig. 1 shows an example of a high-end IPS appliance from Cisco.

Fig. 1: A sample IPS appliance from the Cisco Firepower 9300 Series.

In the 1970s and the early 1980s, administrators had to print out system logs on papers and manually audit the printout [KV02]. The process was clearly 1️⃣ reliant on the auditors’ expertise, 2️⃣ time-consuming, and 3️⃣ too slow to detect attacks in progress.

In the 1980s, storage became cheaper, and intrusion detection programs became available for analysing audit logs online, but the programs could only be run at night when the system’s user load was low [KV02]. Thus, detecting attacks in time remained a challenge.

In the early 1990s, real-time intrusion detection systems (IDSs) that analysed audit logs as the logs were produced became available [KV02].

Since the inception of IDSs, the quality and quantity of audit logs have always been a challenge [KV02]:

Quality

The accuracy (how often the data are correct) and precision (how close the reported values are to the true values) of the data collected are crucial.

Inaccurate or imprecise data could lead to false negatives (illegitimate events misdiagnosed as legitimate) or false positives (legitimate events misdiagnosed as illegitimate).

Quantity

On one hand, not collecting enough data ⇒ an attack could evade detection. For example, network-related data alone cannot help with detecting a malware that does not access any network.

On the other, collecting too much data (from too many sources and/or too frequently) ⇒ storage could run out and processing could take too long.

Effective detection of attacks depends on capturing all relevant data at sufficiently fine time scales.

An IDS is meant to detect [KV02]:

Misuses

These are abuses and attacks of known patterns that can be encoded in computer-interpretable rules or signatures.

An abuse is an intentional or unintentional violation of organisational policies.

Anomalies

An anomaly, also called outlier, is a “significant” deviation from some model of normalcy, where “significance” is contextual and can be fluid.

A model of normalcy is called a baseline model and is often challenging to build for a dynamic environment.

Accordingly, intrusion detection algorithms can be classified as [SM07; YT11, p. 2; BK14, p. 4; Led22; Pal22]:

Rule-based / signature-based

A rule specifies the conditions of legitimacy of an event, typically with the help of signatures.

Signatures can be

  • exploit-facing, e.g., malicious byte sequences, email subject headings associated with phishing, email attachments containing executable binaries, traffic going to known malicious domains, scanning of file hashes; or
  • vulnerability-facing, e.g., SSH requests specifying a vulnerable version number, system log entries indicating disablement of auditing.

Signatures can encode violations of organisational policies, e.g., remote login attempts as “root”.

Stateful protocol analysis or deep packet inspection analyses protocols at the application layer to compare vendor-developed profiles of benign protocol activity against observed events to identify deviations [SH09, Jun16]. This is an example of rule-based detection, contrary to the classification in [LRLT13].

As threats grow, the dictionary of signatures necessarily grows, demanding more computational and storage resources accordingly.

Rule-based detection is effective against known threats that can be expressed using a set of rules and signatures.

Rule-based detection is ineffective against known threats that are hard to capture using a finite set of rules and signatures, e.g., multi-stage attacks; as well as previously unknown threats.

Snort is an industry-standard open-source rule-based intrusion prevention software (hence, also an intrusion detection software). It can for example be found in the appliance in Fig. 1.

Anomaly-based / behaviour-based

This is the application of machine learning techniques to determining whether a user or component behaviour is anomalous.

Depends on the prior establishment of a baseline behavioural model.

Can detect previously unknown attacks as long as the attacks manifest as anomalies relative to the baseline model.

Effective at detection but tends to produce excessive false positives.

Behaviour-based detection, when applied to network behaviour, falls into the area of network behaviour analysis.

Definition 3: Network behaviour analysis [SM07, Xu22]

End-to-end process of collecting, extracting, analysing, modelling, and interpreting network behaviour (e.g., distributed denial of service, worm, backdoor, policy violation) of end systems and network applications from a large volume of network traffic data such as TCP/IP data packets and network flows.

A network behaviour analysis pipeline typically consists of these steps [Xu22, Fig. 2.1]: 1️⃣ network traffic data collection, 2️⃣ data storage and preprocessing, 3️⃣ behavioural feature selection and exploration, 4️⃣ analysis and modeling, 5️⃣ behavioural insights and applications.

Depending on its type, an IDS can comprise several types of components, as shown in Fig. 2: sensors/agents (which monitor and analyse network activities and may also perform preventive actions), management servers, database servers, user and administrator consoles, and management networks [SM07].

There is more than one way to classify IDSs. See the attachment for different classifications of IDSs.

Fig. 2: IDS components. In this context “sensor” is synonymous with “agent”.

Watch the following LinkedIn Learning video for a quick summary of IDS:

What is an IDS? from Protecting Your Network with Open Source Software by Jungwoo Ryoo

References

[BE07] A. R. Baker and J. Esler (eds.), Snort IDS and IPS Toolkit, Syngress, 2007. https://doi.org/10.1016/B978-1-59749-099-3.X5000-9.
[BK14] D. K. Bhattacharyya and J. K. Kalita, Network Anomaly Detection: A Machine Learning Perspective, CRC Press, 2014. https://doi.org/10.1201/b15088.
[FGCMF21] M. Fuentes-García, J. Camacho, and G. Maciá-Fernández, Present and future of network security monitoring, IEEE Access 9 (2021), 112744–112760. https://doi.org/10.1109/ACCESS.2021.3067106.
[Gar22] Gartner, Unified Threat Management (UTM), Information Technology Glossary, 2022, accessed 23 Dec 2022. Available at https://www.gartner.com/en/information-technology/glossary/unified-threat-management-utm.
[HH05] S. Hansman and R. Hunt, A taxonomy of network and computer attacks, Computers & Security 24 no. 1 (2005), 31–43. https://doi.org/10.1016/j.cose.2004.06.011.
[JDR+11] A. Johnson, K. Dempsey, R. Ross, S. Gupta, and D. Bailey, Guide for security-focused configuration management of information systems, NISP Special Publication 800-128, August 2011. https://doi.org/10.6028/NIST.SP.800-128.
[Jun16] Juniper Networks, Learn about intrusion detection and prevention, 2016. Available at https://www.juniper.net/documentation/en_US/learn-about/LA_IntrusionDetectionandPrevention.pdf.
[KV02] R. Kemmerer and G. Vigna, Intrusion detection: a brief history and overview, Computer 35 no. 4 (2002), supl27–supl30. https://doi.org/10.1109/MC.2002.1012428.
[KGVK19] A. Khraisat, I. Gondal, P. Vamplew, and J. Kamruzzaman, Survey of intrusion detection systems: techniques, datasets and challenges, Cybersecurity 2 no. 1 (2019), 20. https://doi.org/10.1186/s42400-019-0038-7.
[Led22] J. Ledesma, IDS vs. IPS: What Organizations Need to Know, Varonis Inside Out Security Blog, June 2022. Available at https://www.varonis.com/blog/ids-vs-ips.
[LRLT13] H.-J. Liao, C.-H. Richard Lin, Y.-C. Lin, and K.-Y. Tung, Intrusion detection system: A comprehensive review, Journal of Network and Computer Applications 36 no. 1 (2013), 16–24. https://doi.org/10.1016/j.jnca.2012.09.004.
[LDVH+18] L. Liu, O. De Vel, Q.-L. Han, J. Zhang, and Y. Xiang, Detecting and preventing cyber insider threats: A survey, IEEE Communications Surveys & Tutorials 20 no. 2 (2018), 1397–1417. https://doi.org/10.1109/COMST.2018.2800740.
[Mav20] N. Mavis, Snort 101, YouTube video by Cisco Talos Intelligence Group, February 2020. Available at https://youtu.be/W1pb9DFCXLw.
[NDP18] J. Navarro, A. Deruyver, and P. Parrend, A systematic survey on multi-step attack detection, Computers & Security 76 (2018), 214–249. https://doi.org/10.1016/j.cose.2018.03.001.
[Pal22] Palo Alto Networks, What is an intrusion prevention system?, Cyberpedia, 2022, accessed 21 Dec 2022. Available at https://www.paloaltonetworks.com/cyberpedia/what-is-an-intrusion-prevention-system-ips.
[SH09] K. Scarfone and P. Hoffman, Guidelines on firewalls and firewall policy, NIST Special Publication 800-41 Revision 1, September 2009. Available at https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-41r1.pdf.
[SM07] K. Scarfone and P. Mell, Guide to Intrusion Detection and Prevention Systems (IDPS), NIST Special Publication 800-94, 2007. Available at https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-94.pdf.
[Sno20] Snort, SNORT® Users Manual 2.9.16, 2020. Available at https://www.snort.org/documents/snort-users-manual-2-9-16-html.
[Sno23] Snort, Shared Object Rules, Snort FAQ, 2023, accessed 3 Feb 2023. Available at https://www.snort.org/faq/shared-object-rules.
[Via22] Viasat, KA-SAT Network cyber attack overview, Viasat corporate news, March 2022. Available at https://news.viasat.com/blog/corporate/ka-sat-network-cyber-attack-overview.
[Xu22] K. Xu, Network Behavior Analysis: Measurement, Models, and Applications, Springer Singapore, 2022. https://doi.org/10.1007/978-981-16-8325-1.
[YT11] Z. Yu and J. J. Tsai, Intrusion Detection: A Machine Learning Approach, Electrical and Computer Engineering, Imperial College Press, 2011.

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Intrusion detection systems: classifications

by Yee Wei Law - Monday, 27 February 2023, 12:02 PM
 
See attachment 👇.

J

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JTAG

by Yee Wei Law - Wednesday, 29 March 2023, 10:18 AM
 

The increasing usage of cutting-edge technologies in safety-critical applications leads to strict requirements on the detection of defects both at the end of manufacturing and in the field [VDSDN+19].

Besides scan chains, test access ports (TAPs) and associated protocols constitute the fundamental test mechanism [VDSDN+19].

Among the earliest standards for test access ports is IEEE Std 1149.1a-1993, first drafted by the Joint Test Action Group (JTAG) in the late 1980s, and then standardised by the IEEE in the early 1990s [IEEE13].

  • The most recent edition of the standard is the 444 pages-long IEEE Std 1149.1-2013 [IEEE13].
  • This standard defines a test access port and boundary scan architecture for 1️⃣ digital integrated circuits and for 2️⃣ the digital portions of mixed analog/digital integrated circuits.
  • The architecture of boundary scan in Fig. 1 is responsible for controlling scan chains through a JTAG interface and an embedded hardware module [BT19, Sec. 3.6.3].
  • The technique of boundary scan involves the inclusion of a shift-register stage (contained in a boundary-scan register cell, see Fig. 2) adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan testing principles [IEEE13, Sec. 1.2.3].
  • Instructions (not states) are loaded into the instruction register (IR), and depending on the instruction, a different data register (DR) is connected between the TDI and TDO terminals; for example, the BYPASS instruction connects a single flip-flop between the TDI and TDO ports [VDSDN+19, p. 96].

Fig. 1: The boundary scan architecture [BT19, FIGURE 3.19]. Note: TDI = test data input; TMS = test mode select; TCK = test clock input; TRST = test reset; TDO = test data output.

The boundary-scan register cells for the pins of a component are interconnected to form a shift-register chain around the border of the design, and this path is provided with serial input and output connections as well as appropriate clock and control signals [IEEE13, Sec. 1.2.3].

Fig. 2: A sample boundary-scan register cell [IEEE13, Figure 1-1].

If used for an input, data can either be loaded into the scan register from the input pin through the “Signal In” port, or be driven from the register through the “Signal Out” port of the cell into the core of the component design, depending on the control signals applied to the multiplexers (see Fig. 1).

If used for an an output, data can either be loaded into the scan register from the core of the component, or be driven from the register to an output pin.

The TAP controller in Fig. 1 implements the 16-state finite state machine in Fig. 3.

For example, Select-DR-Scan is a temporary controller state (i.e., the next rising edge of TCK makes the controller exit this state) in which all test data registers (DRs) selected by the current instruction retain their previous state [IEEE13, p. 26].

  • If TMS is held low and a rising edge is applied to TCK, the controller enters the Capture-DR state and a scan sequence for the selected test data register is initiated.
  • If TMS is held high and a rising edge is applied to TCK, the controller enters the Select-IR-Scan state.
  • The instruction does not change while the TAP controller is in this state.
Fig. 3: The standard TAP controller state diagram [IEEE13, Figure 6-1].

Operationally speaking, the most important consideration for a security analyst, when assessing the security of a device, is finding a JTAG interface. Standard tools such as the Bus Pirate, JTAGulator and Open On-Chip Debugger (OpenOCD) can then be used to probe the device through this interface.

Watch the following tutorial on YouTube:

References

[BT19] S. Bhunia and M. Tehranipoor, Hardware Security: A Hands-On Learning Approach, Morgan Kaufmann, 2019. https://doi.org/10.1016/C2016-0-03251-5.
[IEEE13] IEEE Computer Society, IEEE Standard for Test Access Port and Boundary-Scan Architecture: IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001), 2013. https://doi.org/10.1109/IEEESTD.2013.6515989.
[RM19] P. H. N. Rajput and M. Maniatakos, JTAG: A Multifaceted Tool for Cyber Security, in 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, pp. 155–158. https://doi.org/10.1109/IOLTS.2019.8854430.
[RK10] K. Rosenfeld and R. Karri, Attacks and Defenses for JTAG, IEEE Design & Test of Computers 27 no. 1 (2010), 36–47. https://doi.org/10.1109/MDT.2010.9.
[VDSDN+19] E. Valea, M. Da Silva, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, A Survey on Security Threats and Countermeasures in IEEE Test Standards, IEEE Design & Test 36 no. 3 (2019), 95–116. https://doi.org/10.1109/MDAT.2019.2899064.
[VL18] G. Vishwakarma and W. Lee, Exploiting JTAG and Its Mitigation in IOT: A Survey, Future Internet 10 no. 12 (2018). https://doi.org/10.3390/fi10120121.


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